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EL5171, EL5371
Data Sheet February 16, 2005 FN7307.5
250MHz Differential Twisted-Pair Drivers
The EL5171 and EL5371 are single and triple bandwidth amplifiers with an output in differential form. They are primarily targeted for applications such as driving twistedpair lines in component video applications. The input signal is single-ended and the outputs are always in differential form. On the EL5171 and EL5371, two feedback inputs provide the user with the ability to set the gain of each device (stable at minimum gain of one). For a fixed gain of two, please see EL5170 and EL5370. The output common mode level for each channel is set by the associated VREF pin, which have a -3dB bandwidth of over 50MHz. Generally, these pins are grounded but can be tied to any voltage reference. All outputs are short circuit protected to withstand temporary overload condition. The EL5171 and EL5371 are specified for operation over the full -40C to +85C temperature range.
Features
* Fully differential outputs and feedback * Input range 2.3V typ. * 250MHz 3dB bandwidth * 800V/s slew rate * Low distortion at 5MHz * Single 5V or dual 5V supplies * 90mA maximum output current * Low power - 8mA per channel * Pb-Free available (RoHS compliant)
Applications
* Twisted-pair driver * Differential line driver * VGA over twisted-pair * ADSL/HDSL driver * Single ended to differential amplification
Ordering Information
PART NUMBER EL5171IS EL5171IS-T7 EL5171IS-T13 EL5171ISZ (See Note) EL5171ISZ-T7 (See Note) EL5171ISZ-T13 (See Note) EL5371IU EL5371IU-T7 EL5371IU-T13 PACKAGE 8-Pin SO 8-Pin SO 8-Pin SO 8-Pin SO (Pb-free) 8-Pin SO (Pb-free) 8-Pin SO (Pb-free) 28-Pin QSOP 28-Pin QSOP 28-Pin QSOP TAPE & REEL 7" 13" 7" 13" 7" 13" PKG. DWG. # MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0040 MDP0040 MDP0040
* Transmission of analog signals in a noisy environment
Pinouts
EL5171 (8-PIN SO) TOP VIEW
FBP 1 IN+ 2 REF 3 FBN 4 + 8 OUT+ 7 VS6 VS+ 5 OUTNC 1 INP1 2 INN1 3 REF1 4 NC 5 INP2 6 INN2 7 REF2 8 NC 9 INP3 10 INN3 11 REF3 12 NC 13 EN 14 + + + -
EL5371 (28-PIN QSOP) TOP VIEW
28 OUT1 27 FBP1 26 FBN1 25 OUT1B 24 VSP 23 VSN 22 OUT2 21 FBP2 20 FBN2 19 OUT2B 18 OUT3 17 FBP3 16 FBN3 15 OUT3B
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
EL5171, EL5371
Absolute Maximum Ratings (TA = 25C)
Supply Voltage (VS+ to VS-) . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V Maximum Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . 60mA Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +135C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER AC PERFORMANCE BW -3dB Bandwidth
VS+ = +5V, VS- = -5V, TA = 25C, VIN = 0V, RLD = 1k, RF = 0, RG = OPEN, CLD = 2.7pF, Unless Otherwise Specified DESCRIPTION CONDITIONS MIN TYP MAX UNIT
AV = 1, CLD = 2.7pF AV = 2, RF = 500, CLD = 2.7pF AV = 10, RF = 500, CLD = 2.7pF
250 60 10 50 600 540 800 700 10 20 100 1000 1000
MHz MHz MHz MHz V/s V/s ns ns MHz MHz V/s V/s nV/Hz pA/Hz dBc dBc dBc dBc % dB
BW SR
0.1dB Bandwidth Slew Rate (EL5171) Slew Rate (EL5371)
AV = 1, CLD = 2.7pF VOUT = 3VP-P, 20% to 80% VOUT = 3VP-P, 20% to 80% VOUT = 2VP-P
TSTL TOVR GBWP
Settling Time to 0.1% Output Overdrive Recovery Time Gain Bandwidth Product
VREFBW (-3dB) VREF -3dB Bandwidth VREFSR+ VREFSRVN IN HD2 VREF Slew Rate - Rise VREF Slew Rate - Fall Input Voltage Noise Input Current Noise Second Harmonic Distortion
AV =1, CLD = 2.7pF VOUT = 2VP-P, 20% to 80% VOUT = 2VP-P, 20% to 80% at 10kHz at 10kHz VOUT = 2VP-P, 5MHz VOUT = 2VP-P, 20MHz
50 90 50 26 2 -94 -94 -77 -75 0.1 0.5 90
HD3
Third Harmonic Distortion
VOUT = 2VP-P, 5MHz VOUT = 2VP-P, 20MHz
dG d eS
Differential Gain at 3.58MHz Differential Phase at 3.58MHz Channel Separation
RL = 300, AV = 2 RL = 300, AV = 2 at f = 1MHz
INPUT CHARACTERISTICS VOS IIN IREF RIN CIN DMIR CMIR+ CMIRVREFIN + Input Referred Offset Voltage Input Bias Current (VIN+, VIN-) Input Bias Current (VREF) Differential Input Resistance Differential Input Capacitance Differential Mode Input Range Common Mode Positive Input Range at VIN+, VINTested only for EL5371 2.1 3.1 -14 0.5 1.5 -6 1.3 300 1 2.3 3.4 -4.5 3.5 3.8 -4.2 2.5 25 -3 4 mV A A k pF V V V V
Common Mode Negative Input Range at VIN+, VIN- Tested only for EL5371 Positive Reference Input Voltage Range (EL5371) VIN+ = VIN- = 0V
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EL5171, EL5371
Electrical Specifications
PARAMETER VREFIN VREFOS CMRR Gain VS+ = +5V, VS- = -5V, TA = 25C, VIN = 0V, RLD = 1k, RF = 0, RG = OPEN, CLD = 2.7pF, Unless Otherwise Specified (Continued) DESCRIPTION Negative Reference Input Voltage Range (EL5371) Output Offset Relative to VREF (EL5371) Input Common Mode Rejection Ratio (EL5371) Gain Accuracy VIN = 2.5V VIN = 1 (EL5171) VIN = 1 (EL5371) OUTPUT CHARACTERISTICS VOUT Output Voltage Swing RL = 500 to GND (EL5171) RL = 500 to GND (EL5371) IOUT(Max) Maximum Output Current RL = 10, VIN = 3.24 (EL5171) RL = 10, VIN = 3.24 (EL5371) ROUT SUPPLY VSUPPLY IS(ON) IS(OFF)+ IS(OFF)PSRR Supply Operating Range Power Supply Current - Per Channel Positive Power Supply Current - Disabled (EL5371) EN pin tied to 4.8V Negative Power Supply Current - Disabled (EL5371) Power Supply Rejection Ratio VS from 4.5V to 5.5V (EL5171) VS from 4.5V to 5.5V (EL5371) ENABLE (EL5371 ONLY) tEN tDS VIH VIL IIH-EN IIL-EN Enable Time Disable Time EN Pin Voltage for Power-Up EN Pin Voltage for Shut-Down EN Pin Input Current High EN Pin Input Current Low At VEN = 5V At VEN = 0V -10 VS+ 0.5 122 -8 130 215 0.95 VS+ 1.5 ns s V V A A -200 70 65 VS+ to VS4.75 6.8 7.5 1.7 -120 84 83 11 8.2 10 V mA A A dB dB Output Impedance 3.6 70 50 3.4 3.9 90 70 130 120 90 V V mA mA m 70 0.981 0.978 CONDITIONS VIN+ = VIN- = 0V MIN TYP -3.3 60 82 0.996 0.993 1.011 1.008 MAX -3 100 UNIT V mV dB V V
Pin Descriptions
EL5171 1 2 3 4 5 6 7 8 EL5371 17, 21, 27 2, 6, 10 3, 7, 11 16, 20, 26 15, 19, 25 24 23 18, 22, 28 1, 5, 9, 13 4, 8, 12 14 PIN NAME FBP1, 2, 3 INP1, 2, 3 INN1, 2, 3 FBN1, 2, 3 OUT1B, 2B, 3B VSP VSN OUT1, 2, 3 NC REF1, 2, 3 EN PIN FUNCTION Feedback from non-inverting output Non-inverting inputs Inverting inputs, note that on EL5171, this pin is also the REF pin Feedback from inverting output Inverting outputs Positive supply Negative supply Non-inverting outputs No connects, grounded for best crosstalk performance Reference input, sets common-mode output voltage ENABLE
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FN7307.5 February 16, 2005
Connection Diagrams
EL5171
RF1 -5V 1 FBP INP REF RS1 50 RS1 50 RG 2 INP 3 REF 4 FBN OUT 8 VSN 7 VSP 6 OUTB 5 RF3 +5V CL2 5pF RLD 1k OUTB CL1 5pF OUT
4
INP1 INN1 REF1 INP2 INN2 REF2 INP3 INN3 REF3 RSP1 50
FN7307.5 February 16, 2005
EL5371
+5V
EL5171, EL5371
1 NC 2 INP1 3 INN1 4 REF1 5 NC 6 INP2 7 INN2 8 REF2 9 NC 10 INP3 11 INN3 12 REF3 RSN1 50 RSR1 50 RSP2 50 RSN2 50 RSR2 50 RSP3 50 RSN3 50 RSR3 50 13 NC 14 EN
OUT1 28 FBP1 27 FBN1 26 OUT1B 25 VSP 24 VSN 23 OUT2 22 FBP2 21 FBN2 20 OUT2B 19 OUT3 18 FBP3 17 FBn3 16 OUT3B 15 -5V
RF RG RLD1 1k
RF
RF RG RLD2 1k RF
RF RG RLD3 1k
RF
CL1 5pF
CL1B 5pF
CL2 5pF
CL2B 5pF
CL3 5pF
CL3B 5pF
ENABLE
EL5171, EL5371 Typical Performance Curves
AV = 1, RLD = 1k, CLD = 2.7pF 4 3 2 MAGNITUDE (dB) 1 0 -1 -2 -3 -4 -5 -6 1M 10M 100M 1G VOP-P = 1VP-P VOP-P = 200mV NORMALIZED MAGNITUDE (dB) 4 3 2 1 0 -1 -2 -3 -4 -5 -6 1M 10M 100M 1G AV = 10 AV = 5 AV = 2 AV = 1 RLD = 1k, CLD = 2.7pF
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 1. FREQUENCY RESPONSE
AV = 1, CLD = 2.7pF 4 3 NORMINALIZED GAIN (dB) 2
FIGURE 2. FREQUENCY RESPONSE FOR VARIOUS GAIN
AV = 1, RLD = 1k 5 4 3 MAGNITUDE (dB) CLD = 56pF CLD = 34pF CLD = 23pF
1 0 -1 -2 -3 -4 -5 -6 1M 10M 100M 1G RLD = 200 RLD = 1k RLD = 500
2 1 0 -1 -2 -3 -4 -5 1M 10M 100M CLD = 9pF CLD = 2.7pF
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 3. FREQUENCY RESPONSE vs RLD
FIGURE 4. FREQUENCY RESPONSE vs CLD
AV = 2, RF = 1k, CLD = 2.7pF 10 9 NORMALIZED GAIN (dB) 8 7 6 5 4 3 2 1 RLD = 200 RLD = 500 RLD = 1k
AV = 2, RLD = 1k, CLD = 2.7pF 10 9 NORMALIZED GAIN (dB) 8 7 6 5 4 3 2 1 0 1M 10M FREQUENCY (Hz) 100M 400M RF = 200 RF = 500 RF = 1k
0 1M
10M FREQUENCY (Hz)
100M
400M
FIGURE 5. FREQUENCY RESPONSE
FIGURE 6. FREQUENCY RESPONSE vs RLD
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FN7307.5 February 16, 2005
EL5171, EL5371 Typical Performance Curves
5 4 3 MAGNITUDE (dB) IMPEDENCE () 2 1 0 -1 -2 -3 -4 -5 100K 1M 10M FREQUENCY (Hz) 100M 0.1 10K 100K 1M FREQUENCY (Hz) 10M 100M 10
(Continued)
100
1
FIGURE 7. FREQUENCY RESPONSE - VREF
FIGURE 8. OUTPUT IMPEDANCE vs FREQUENCY
0 -10 -20 CMRR (dB) PSRR (dB) -30 -40 -50 -60 -70 -80 -90 1K 10K 100K 1M 10M 100M PSRR+ PSRR-
100 90 80 70 60 50 40 30 20 10 0 100K 1M 10M FREQUENCY (Hz) 100M 1G
FREQUENCY (Hz)
FIGURE 9. PSRR vs FREQUENCY
FIGURE 10. CMRR vs FREQUENCY
1K VOLTAGE NOISE (nV/Hz), CURRENT NOISE (pA/Hz)
-30 -40
100 GAIN (dB) EN 10 IN 1 10 100 1K 10K 100K 1M 10M
-50 -60 -70 -80 -90 -100 100K CH1 <=> CH3 CH1 <=> CH2, CH2 <=> CH3
1M
10M FREQUENCY (Hz)
100M
1G
FREQUENCY (Hz)
FIGURE 11. VOLTAGE AND CURRENT NOISE vs FREQUENCY
FIGURE 12. CHANNEL ISOLATION vs FREQUENCY
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FN7307.5 February 16, 2005
EL5171, EL5371 Typical Performance Curves
VS = 5V, AV = 1, RLD = 1k -50 -55 -60 DISTORTION (dB) -65 -70 -75 -80 -85 -90 -95 -100 1 1.5 2 2.5 3
HD3 (f = 5MHz)
HD3 (f = 20MHz)
(Continued)
VS = 5V, AV = 1, RLD = 1k -50 -55 -60 DISTORTION (dB) -65 -70 -75 -80 -85 -90 4 4.5 5 -95 1 2
Hz) HD2 (f = 5M
HD2 (f = 20MHz)
HD3 (f = 20MH z)
HD3 (f = 5MHz)
HD2 (f
= 20M
Hz )
( HD2
f=
z) 5M H
3.5
3
4
5
6
7
8
9
10
VOP-P, DM (V)
VOP-P, DM (V)
FIGURE 13. HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT VOLTAGE
VS = 5V, AV = 1, VOP-P, DM = 1V -50 -55 DISTORTION (dB)
HD
FIGURE 14. HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT VOLTAGE
VS = 5V, AV = 2, VOP-P, DM = 2V -40 -50 DISTORTION (dB) HD3 (f = 20MHz) HD3 (f = 5MHz)
-60 -65 -70 -75 -80 -85 -90 -95
3
(f
HD 3
= 20 M Hz
(f
=
-60 -70 -80 -90
5M
Hz )
HD
)
2 (f
=2
HD2 (f
0M
HD2 (f
Hz
= 20MH
z)
)
= 5M Hz)
HD2 (f = 5MHz)
-100 100
-100 200 200 300 400 500 600 700 800 900 1000 RLD ()
300
400
500
600 RLD ()
700
800
900
1000
FIGURE 15. HARMONIC DISTORTION vs RLD
VS = 5V, RLD = 1k, VOP-P, DM = 1V for AV = 1, VOP-P, DM = 2V for AV = 2 HD3 (AV = 1)
FIGURE 16. HARMONIC DISTORTION vs RLD
-40 -50 DISTORTION (dB) -60 -70 -80 -90 -100
3 HD
(AV
=2
)
HD2 (AV =
2)
HD2 (AV
= 1)
50mV/DIV
0
10
20
30
40
50
60
FREQUENCY (MHz)
10ns/DIV
FIGURE 17. HARMONIC DISTORTION vs FREQUENCY
FIGURE 18. SMALL SIGNAL TRANSIENT RESPONSE
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FN7307.5 February 16, 2005
EL5171, EL5371 Typical Performance Curves
(Continued)
M = 100ns, CH1 = 500mV/DIV, CH2 = 5V/DIV
0.5V/DIV
CH1 CH2
10ns/DIV
100ns/DIV
FIGURE 19. LARGE SIGNAL TRANSIENT RESPONSE
M = 200ns, CH1 = 500mV/DIV, CH2 = 5V/DIV 1.2 POWER DISSIPATION (W) 1 0.8
FIGURE 20. ENABLED RESPONSE
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.010W QSOP28 JA=99C/W 625mW 0.6 0.4 0.2 0 SO8 JA=160C/W
CH1
CH2
200ns/DIV
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (C)
FIGURE 21. DISABLED RESPONSE
FIGURE 22. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.266W 909mW
1.4 POWER DISSIPATION (W) 1.2 1 0.8 0.6 0.4 0.2 0
QSOP28 JA=79C/W
SO8 JA=110C/W
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (C)
FIGURE 23. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
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FN7307.5 February 16, 2005
EL5171, EL5371 Simplified Schematic
VS+ R3 R7 R4 R8
R1
R2
IN+
IN-
FBP
FBN
VB1
OUT+ RCD RCD REF R9 R10
CC
VB2 CC R5 VSR6
OUT-
Description of Operation and Application Information
Product Description
The EL5171 and EL5371 are wide bandwidth, low power and single ended to differential output amplifiers. The EL5171 is a single channel differential amplifier. Since the IN- pin and REF pin are tired together internally, the EL5171 can be used as a single ended to differential converter. The EL5371 is a triple channel differential amplifier. The EL5371 have a separate IN- pin and REF pin for each channel. It can be used as single/differential ended to differential converter. The EL5171 and EL5371 are internally compensated for closed loop gain of +1 of greater. Connected in gain of 1 and driving a 1k differential load, the EL5171 and EL5371 have a -3dB bandwidth of 250MHz. Driving a 200 differential load at gain of 2, the bandwidth is about 30MHz. The EL5371 is available with a power down feature to reduce the power while the amplifier is disabled.
Differential and Common Mode Gain Settings
For EL5171, since the IN- pin and REF pin are bounded together as the REF pin in an 8-pin package, the signal at the REF pin is part of the common mode signal and also part of the differential mode signal. For the true balance differential outputs, the REF pin must be tired to the same bias level as the IN+ pin. For a 5V supply, just tire the REF pin to GND if the IN+ pin is biased at 0V with a 50 or 75 termination resistor. For a single supply application, if the IN+ is biased to half of the rail, the REF pin should be biased to half of the rail also. The gain setting for EL5171 is:
R F1 + R F2 V ODM = V IN + x 1 + --------------------------- RG 2RF V ODM = V IN + x 1 + ---------- RG V OCM = V REF = 0V
Input, Output, and Supply Voltage Range
The EL5171 and EL5371 have been designed to operate with a single supply voltage of 5V to 10V or a split supplies with its total voltage from 5V to 10V. The amplifiers have an input common mode voltage range from -4.5V to 3.4V for 5V supply. The differential mode input range (DMIR) between the two inputs is from -2.3V to +2.3V. The input voltage range at the REF pin is from -3.3V to 3.8V. If the input common mode or differential mode signal is outside the above-specified ranges, it will cause the output signal distorted. The output of the EL5171 and EL5371 can swing from -3.9V to +3.9V at 1k differential load at 5V supply. As the load resistance becomes lower, the output swing is reduced.
Where: * VREF = 0V * RF1 = RF2 = RF EL5371 has a separate IN- pin and REF pin. It can be used as a single/differential ended to differential converter. The voltage applied at REF pin can set the output common mode voltage and the gain is one.
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FN7307.5 February 16, 2005
EL5171, EL5371
The gain setting for EL5371 is:
R F1 + R F2 V ODM = ( V IN + - V IN - ) x 1 + --------------------------- RG 2R F V ODM = ( V IN + - V IN - ) x 1 + ---------- RG V OCM = V REF
Driving Capacitive Loads and Cables
The EL5171 and EL5371 can drive 50pF differential capacitor in parallel with 1k differential load with less than 5dB of peaking at gain of +1. If less peaking is desired in applications, a small series resistor (usually between 5 to 50) can be placed in series with each output to eliminate most peaking. However, this will reduce the gain slightly. If the gain setting is greater than 1, the gain resistor RG can then be chosen to make up for any gain loss which may be created by the additional series resistor at the output. When used as a cable driver, double termination is always recommended for reflection-free performance. For those applications, a back-termination series resistor at the amplifier's output will isolate the amplifier from the cable and allow extensive capacitive drive. However, other applications may have high capacitive loads without a back-termination resistor. Again, a small series resistor at the output can help to reduce peaking.
Where: * RF1 = RF2 = RF
RF1
FBP VIN+ VINVREF RG IN+ INREF FBN RF2 V OV O+
Disable/Power-Down (for EL5371 only)
The EL5371 can be disabled and placed its outputs in a high impedance state. The turn off time is about 0.95s and the turn on time is about 215ns. When disabled, the amplifier's supply current is reduced to 1.7A for IS+ and 120A for IStypically, thereby effectively eliminating the power consumption. The amplifier's power down can be controlled by standard CMOS signal levels at the ENABLE pin. The applied logic signal is relative to VS+ pin. Letting the EN pin float or applying a signal that is less than 1.5V below VS+ will enable the amplifier. The amplifier will be disabled when the signal at EN pin is above VS+ - 0.5V.
FIGURE 24.
Choice of Feedback Resistor and Gain Bandwidth Product
For applications that require a gain of +1, no feedback resistor is required. Just short the OUT+ pin to FBP pin and OUT- pin to FBN pin. For gains greater than +1, the feedback resistor forms a pole with the parasitic capacitance at the inverting input. As this pole becomes smaller, the amplifier's phase margin is reduced. This causes ringing in the time domain and peaking in the frequency domain. Therefore, RF has some maximum value that should not be exceeded for optimum performance. If a large value of RF must be used, a small capacitor in the few Pico farad range in parallel with RF can help to reduce the ringing and peaking at the expense of reducing the bandwidth. The bandwidth of the EL5171 and EL5371 depends on the load and the feedback network. RF and RG appear in parallel with the load for gains other than +1. As this combination gets smaller, the bandwidth falls off. Consequently, RF also has a minimum value that should not be exceeded for optimum bandwidth performance. For gain of +1, RF = 0 is optimum. For the gains other than +1, optimum response is obtained with RF between 500 to 1k. The EL5171 and EL5371 have a gain bandwidth product of 100MHz for RLD = 1k. For gains 5, its bandwidth can be predicted by the following equation:
Gain x BW = 100MHz
Output Drive Capability
The EL5171 and EL5371 have internal short circuit protection. Its typical short circuit current is 90mA for EL5171 and 70mA for EL5371. If the output is shorted indefinitely, the power dissipation could easily increase such that the part will be destroyed. Maximum reliability is maintained if the output current never exceeds 60mA. This limit is set by the design of the internal metal interconnections.
Power Dissipation
With the high output drive capability of the EL5171 and EL5371. It is possible to exceed the 135C absolute maximum junction temperature under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the application to determine if the load conditions or package types need to be modified for the amplifier to remain in the safe operating area.
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FN7307.5 February 16, 2005
EL5171, EL5371
The maximum power dissipation allowed in a package is determined according to:
T JMAX - T AMAX PD MAX = ------------------------------------------- JA
By setting the two PDMAX equations equal to each other, we can solve the output current and RLD to avoid the device overheat.
Power Supply Bypassing and Printed Circuit Board Layout
As with any high frequency device, a good printed circuit board layout is necessary for optimum performance. Lead lengths should be as sort as possible. The power supply pin must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VS- pin is connected to the ground plane, a single 4.7F tantalum capacitor in parallel with a 0.1F ceramic capacitor from VS+ to GND will suffice. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. In this case, the VS- pin becomes the negative supply rail. For good AC performance, parasitic capacitance should be kept to minimum. Use of wire wound resistors should be avoided because of their additional series inductance. Use of sockets should also be avoided if possible. Sockets add parasitic inductance and capacitance that can result in compromised performance. Minimizing parasitic capacitance at the amplifier's inverting input pin is very important. The feedback resistor should be placed very close to the inverting input pin. Strip line design techniques are recommended for the signal traces.
Where: * TJMAX = Maximum junction temperature * TAMAX = Maximum ambient temperature * JA = Thermal resistance of the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the load, or:
V O PD = i x V S x I SMAX + V S x ----------- R LD
Where: * VS = Total supply voltage * ISMAX = Maximum quiescent supply current per channel * VO = Maximum differential output voltage of the application * RLD = Differential load resistance * ILOAD = Load current * i = Number of channels
Typical Applications
RF
FBP IN+ RT RG INREF FBN RF EL5171/ EL5371
50
TWISTED PAIR
IN+ EL5172/ EL5372
50 ZO = 100 INREF
VO
RFR RGR
FIGURE 25. TWISTED PAIR CABLE RECEIVER
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FN7307.5 February 16, 2005
EL5171, EL5371
As the signal is transmitted through a cable, the high frequency signal will be attenuated. One way to compensate
RF
this loss is to boost the high frequency gain at the receiver side.
Gain (dB)
FBP RT 75 RGC CL RG IN+ INREF FBN RF fL fH frequency VOVO+
2R F DC Gain = 1 + ---------RG 2R F ( HF )Gain = 1 + -------------------------R G || R GC
1 f L -----------------------2R G C C 1 f H ---------------------------2R GC C C FIGURE 26. TRANSMIT EQUALIZER
SO Package Outline Drawing
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FN7307.5 February 16, 2005
EL5171, EL5371 QSOP Package Outline Drawing
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at http://www.intersil.com/design/packages/index.asp
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 13
FN7307.5 February 16, 2005

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